Liner deposition is a necessary unit operation in integrated circuit fabrication. “Liners” include diffusion barrier layers, seed layers, capping layers, and the like. They are made from metal-containing compounds or metals themselves, such as copper, tungsten, tantalum, titanium, and nitrides of these. As device features shrink well below the 0.5 micrometer scale, there is little room for imperfection in the deposited liners. The challenge is particularly great in damascene processes and other processes where the liner must conformally cover high aspect ratio sub-0.5 micrometer scale trenches, vias, or other recesses. Not only must the liner conformally cover the recess, but it must also adhere well to the underlying dielectric or other support material, be relatively free of impurities and, for many applications, have a stable crystallographic morphology. In cases where the liner carries part of the electrical current flowing in the interconnect, low electrical resistance is also desired.
Current film deposition processes have difficulty meeting all these requirements. Physical vapor deposition techniques can produce high quality, high purity, low resistance liners. But PVD liners are insufficiently conformal for processes employing very narrow trenches having high aspect ratios. Chemical vapor deposition and atomic layer deposition can produce superbly conformal layers, but those layers are often hampered by impurities and poor morphology—frequently resulting from organic decomposition products of chemical vapor deposition precursors. The relatively high resistivity of chemical vapor deposition films is a significant downside. Further, the relatively high process temperatures employed with CVD can limit its application.
What is needed therefore is an improved liner deposition process to meet the needs of modern integrated circuit fabrication.